Microprocessors often include modules for storing instructions and data and/or for operating on instructions and data. The modules include storage or memory modules and functional modules. Memory modules include registers, random access memory, read only memory, etc. Functional modules include counters, finite state machines, output of logic functions, etc. The microprocessor accesses the modules through the use of a control system including a register master connected with one or more register slaves. One or more of the register slaves are associated with, and provide the microprocessor interface to, a module. That is, the microprocessor transmits an address to the register master and specifies whether a read of data located at the provided address is to be performed or a write of data provided by the microprocessor to the provided address is to be performed. The register master communicates this information to the register slave.
The register slave then requests an access to a particular location, e.g., a memory location if the module is a memory module, a logic function if the module is a functional module, specified by the provided address. The access type is specified by a read or write control signal. The register slave interface with the module varies based on the control signals, i.e., the control and data signals transmitted across the register slave-module interface varies depending on the module to which the register slave is interfaced.
In many cases the module access is partitioned into two separate pieces: a master component such as the register master and a slave component such as the register slave. The master component handles interfacing with the microprocessor bus. The slave component is custom configured for each particular module type and handles interfacing with the module. The master component communicates with the slave component using a particular protocol, i.e., timing and order of data and control signals. Each module to be addressed under previous approaches requires design and testing of a new interface between the microprocessor, register master, slave component, and module. Further, for each new module to be interfaced with a microprocessor, design and testing of a corresponding slave component is required. That is, each slave component interface with the master component and the module is designed anew for each new module to which the slave component is interfaced.
Designing anew or redesigning the slave component for each new module incurs increased development time and cost. Further, testing requirements are increased for both functionality (correctness), timing, and corner case condition detection and correction. Further still, increased testing and development frequently requires increased time and cost related to updating testing tools and procedures to account for a new design. Further still, in order to obtain additional functional capabilities in a new design, e.g., testability, additional design and development costs are incurred.